Modern integrated circuits often include a power management modes used for conservation of power. For example, many devices implement a power-down mode in which the integrated circuit conserves power by deactivating input and output buffers, excluding certain buffers for signals needed for exiting the power-down mode. On exiting the power-down mode, the buffers are reactivated and the clock, addresses and decoded commands are distributed to the necessary elements of the device.
Many designs now operate with faster and slower clocks in respective domains on the device. Memory devices for example often include a clock, called a control clock herein, used for command and address logic and other functions on the device, and a data clock used for driving high speed data path circuits and data interfaces on the device. The data clock in such systems may run at a higher frequency than the control clock. Recovery from a power-down mode, and other operations changing power management modes for such devices, can require reactivating circuits in both the control clock domain and circuits in the data clock domain.